Integrated circuits (ICs) typically include a plurality of semiconductor devices and interconnect wiring. Networks of metal interconnect wiring are often used to connect the semiconductor devices from the semiconductor portion of the substrate. Multiple levels of metal interconnect wiring form a plurality of metallization layers above the semiconductor portion of the substrate and are connected together to form a back-end-of-the-line (“BEOL”) interconnect structure. Within such a structure, metal lines run parallel to the substrate in the metallization layers and conductive vias run perpendicular to the substrate between the metallization layers to interconnect the metal lines.
High performance of contemporary ICs may be achieved using a highly conductive metal, such as copper (Cu), as the interconnect metal of the BEOL interconnect structure, which also employs a low dielectric constant material or dielectric material as an interlevel dielectric (ILD) layer or layers to insulate the interconnect wires from each other. To help prevent migration of the interconnect metal into the ILD layer, a barrier-forming material, such as tantalum nitride (TaN), is deposited onto the dielectric material to form a barrier layer. A metal liner material, such as tantalum (Ta) or the like, is deposited overlying the barrier layer to form a metal liner layer to help hold the highly conductive interconnect metal to the barrier layer and the underlying dielectric material. Then, a conductive metal seed layer, such as a layer of copper (Cu) or copper alloy, is formed on the metal liner layer and the highly conductive metal (e.g., Cu) is deposited over the conductive metal seed layer to form a metal interconnect wire. Unfortunately, many conventional approaches for forming the barrier layers for such interconnect structures can (1) damage the underlying dielectric material of the ILD layer, (2) produce non-conformal barrier layers that are too thin or discontinuous particularly along vertical walls or too thick particularly around corners of the ILD layer, and/or (3) form relatively low density barrier layers that have undesirably high resistivity and/or are susceptible to damage by impurities, such as oxygen (O), carbon (C), or the like, that are produced during subsequent deposition of the liner.
Accordingly, it is desirable to provide methods for fabricating integrated circuits including forming barrier layers that are more robust such as for back-end-of-the-line interconnect structures. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.